The present invention relates generally to the field of frequency modification, and more specifically, to the field of controlling frequency synthesis in a CDMA/FM (code division multiple access/frequency modulation) dual-mode cellular telephone.
A phase-locked loop (PLL) is an electronic circuit for providing a signal with a precisely controlled frequency. One example of a typical PLL includes a PLL frequency synthesizer, a low pass filter, and a voltage-controlled oscillator (VCO). One type of prior art PLL frequency synthesizer, such as the MC145170 integrated circuit available from Motorola, includes dividing counters, configuration registers, a phase detector, a lock detector, and a reference signal buffer. Inputs and outputs include, among others, a reference oscillator input and output, a VCO input, a data input, a phase detector output, a lock detector output, and a buffered reference output. The phase detector and lock detector continuously compare signals from the dividing counters which divide signals received through the reference oscillator input and the VCO input according to data received through the data input. The voltage of the signal continuously output through the phase detector output provides an indication of the phase difference between the internal signals from the dividing counters, and the lock detector output provides an indication of when those signals are perfectly in phase with each other.
According to a conventional circuital configuration of a PLL, a low pass filter and a VCO are coupled between the phase detector output and the VCO input of the PLL frequency synthesizer. In one such configuration, a crystal oscillator is coupled across the reference oscillator input and output of the PLL frequency synthesizer. The buffered reference output provides a buffered version of the crystal oscillator reference frequency (or a division thereof) for driving additional PLL frequency synthesizers or clock inputs on other devices, thereby removing the need for additional crystals for those devices. In another configuration, such as one of the above-referenced "additional PLL frequency synthesizers", an external clock source is connected to the reference oscillator input to provide a reference frequency and replace the crystal oscillator. In each of these configurations, the signal at the VCO input of the PLL frequency synthesizer is used as the output frequency of the PLL. Through the control signal which is output through the phase detector output of the PLL frequency synthesizer, the VCO is locked to oscillate at a particular frequency with a particular phase, according to the signal received through the reference oscillator input.
One additional circuital element often used in conjunction with the output of the PLL is an external signal buffer, such as a linearly biased digital inverter, an appropriately biased transistor, etc. A buffer provides enough power to drive subsequent circuital elements without undesirably loading the VCO, isolates the VCO from noise and interference generated by subsequent circuital elements, and, depending on the type of buffer employed, provides a full square wave (digital) output. In order to provide a smaller, less expensive, and simpler design, it would be desirable to omit this extra buffer. Unfortunately, the prior art provides little assistance in this endeavor.
Additionally, in CDMA/FM dual-mode cellular telephones, as well as other multi-mode devices, it is often desirable to be able to conserve power by removing power to various elements not in use. Unfortunately, removing power to many PLL frequency synthesizers would necessitate re-loading data into the various registers of the PLL frequency synthesizer, a process which would require too much time for many applications.
There is, therefore, a need in the industry for a phase-locked loop circuit which addresses these and other related, and unrelated, problems.